In a semiconductor device that operates in synchronization with a clock, such as a synchronous DRAM or the like, in order to operate in synchronization with a system clock supplied from outside, it is necessary to use a variable delay circuit such as a DLL circuit, to accurately adjust delay time of an internal circuit in synchronization with the external clock. For this, various types of adjustment method for the delay time have been proposed.
In particular, Patent Document 1 discloses a variable delay circuit (delay synchronization loop) in which, in order to perform adjustment of the delay time more precisely than by delay time adjustment by changing the number of cascade-connected delay elements, phase delay is increased or decreased more precisely than an increase or decrease of phase delay according to the number of series-connected delay elements by using an input clock signal DCTS having the phase of a reference clock phase variably delayed.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-58275A, which corresponds to US Patent Application Publication No. US2002/0153929A1.